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D-Type Flip Flop

Introduction

The D-type flip-flop is a very very useful circuit component in digital electronics and it is worth spending time to fully understand its operation.

Basic Operation

diagramThe D-type flip-flop looks a lot like a bistable and, in effect, it is a bistable - the output has two stable states and will either remain HIGH or LOW until forced to change. The difference between a D-type flip-flop and simple SET-RESET bistable is the way in which the output(s) are made to change. A D-type flip-flop uses a CLOCK.

The basic block diagram shown has two outputs Q and Q. The SET input will make Q go HIGH and the RESET input will make Q go LOW.

The CLOCK (Ck) and DATA (D) inputs work together. The basic operation is when the CLOCK changes from LOW to HIGH, Q will become the same as DATA at that instant. Or, put another way, on the rising edge of the CLOCK, the value at the DATA input is transferred to the output, Q.

Note: There are four inputs. The SET and RESET inputs take priority over the CLOCK and DATA. Any unused input should always be connected to 0V to ensure reliable operation.


Timing Diagram

Timing Diagram Working through the timing diagram from left to right: Q is initially LOW. When SET goes momentarily HIGH, Q goes HIGH and stays HIGH. When RESET goes momentarily HIGH, Q goes LOW and stays LOW

DATA changes from LOW to HIGH and has no effect on Q - the output does not respond when DATA changes. On the rising edge of the first clock pulse DATA is HIGH and so Q goes HIGH. DATA momentary changes back to LOW and then back to HIGH ... this has no effect on Q. On the rising edge of the second clock pulse DATA is still HIGH and so Q remains HIGH.

On the rising edge of the third clock pulse DATA is LOW and so Q goes LOW. On the rising edge of the 4th and 5th clock pulses DATA is still LOW and so, on each rising edge of the clock, Q remains LOW. On the rising edge of the 6th and final clock pulse DATA is HIGH to Q goes HIGH.

Note that Q is always the opposite of Q. The output can be made HIGH at any time using the SET input as this has priority over the CLOCK and DATA inputs. Similarly the RESET can be used to make the output go LOW at any time.


4013

4013 pinoutThe 4013 IC is a dual D-type flip-flop as shown. The two flip-flops work completely independently of each other.



Useful Circuits

D-type LatchSimple Latch
In this circuit DATA = 1 at all times.

Q is made LOW using the reset button. When the button is pressed RESET = 1 and Q = 0. The circuit will remain in this state until the clock goes HIGH.

On the rising edge, as the clock changes from LOW to HIGH the DATA is transferred to Q therefore, as DATA = 1, Q = 1. The output Q remains HIGH until the circuit is reset.



toggleToggle switch
This circuit uses a single push button to turn an output ON if it is OFF and OFF if it is ON. This is achieved using feedback - a very important point.

Consider starting with Q = 0. Therefore Q = 1 and DATA = 1. When the button is pressed CLOCK receives a rising edge and the value of DATA = 1 is transferred to Q = 1. The output is now ON. AS Q = 1, Q = 0 and DATA = 0. When the button is pressed again DATA = 0 is transferred to Q = 0. The output is now OFF.

Each clock pulse transfers DATA to Q but each clock also changes data to the opposite state. Note the timing - DATA is transferred to Q and then Q changes as a result and then DATA changes ... after the CLOCK has risen.

This is a very useful circuit if you want one button to start something and then the same button to stop it again such as on a stop-watch.



divide by 2Divide by 2 counter
Although the use of this circuit is not immediately obvious, it is very useful later on.

Consider Q = 0 and so Q = 1 and DATA = 1. The first CLOCK pulse changes Q to be HIGH. The next clock pulse changes Q back to being LOW. It takes TWO complete clock cycles to make the output change through one cycle (OFF to ON to OFF again). Therefore the clock input must be at twice the frequency of the output.

This video shows how the divide by two counter functions.


simple timingNote that the toggle circuit and the divide by 2 counter are essentially the same circuit and have the same timing diagram as shown.



D-type Quiz RefereeQuiz referee
In this circuit feedback from Q is used - this is an important point. When the circuit is reset QA and QB are both LOW and both Q outputs are HIGH and therefore both DATA inputs are HIGH. When the CLOCK of flip-flop A receives a rising edge (as button A is pressed) then QA goes HIGH and the corresponding QA goes LOW making DATA on the other flip-flop go LOW. Now flip-flop A has DATA = 1 so pressing button A will simply continue to make QA = 1. As flip-flop B has DATA = 0, pressing button B will continue to make QB = 0. The circuit is now locked with QA = 1 and QB = 0.

The same argument applies if button B is pressed first but in this case QB = 1 and QA = 0. Therefore, whichever button is pressed first sets its output HIGH and locks the circuit. If button A is pressed first, QA goes HIGH and the outputs cannot be changed by pressing either button A or button B. If button B is pressed first, QB goes HIGH and the output cannot be changed by pressing either button A or button B. QA and QB both go LOW when the RESET is pressed.

The circuit works by using feedback from Q to DATA to change the value of DATA once the clock has received a rising edge.



D-type DataLatchData Latch
In this circuit the four inputs (I0 - I3) are connected to the DATA pins on the four flip-flops.

When the common CLOCK is taken HIGH then the input values are transferred to the four outputs (Q0 to Q3) and held.

Even if the inputs subsequently change the outputs remain the same. This is a simple 4-bit memory.