# Astable Circuits

An astable circuit is one that oscillates continuously between two states, it cannot settle into just one state. The period of oscillation is determined by the timing components used. The output is high for some period of time (mark) and low for some period of time (space) - the mark-space ratio is determined by the choice of timing components and the design of the circuit.

For a square wave, a mark-space ratio of 1:1 is required

The period (T) of oscillation is the time for one complete cycle - this is related to the frequency.

## f = 1 / T

### Using the 555 as an astable

The following circuit uses the 555 chip as an astable oscillator.

In operation the output Q is low whilst the capacitor discharges - as this happens pin 7 is held low by the internal circuitry of the 555 IC and so the capacitor discharges through Rb only. The time for this discharge is 0.7RbC (the voltage across the capacitor halves). When the capacitor is sufficiently discharged the output goes high and pin 7 is allowed to float. The capacitor now charges through Ra and Rb and so the time to charge is 0.7 ( Ra + Rb ) C. The mark-space ratio obviously cannot be 1:1. The total time period is given by:

## T = 0.7 ( Ra + 2Rb ) C

The 555 astable is quick and easy to build, the following points should be noted:

• The 555 takes a lot of current as the output changes state. This can affect other ICs using the same power supply. A large value capacitor (47µF shown) connected near to the 555 IC will help to reduce the impact of this problem
• The mark-space ratio cannot be 1:1 - for a true square wave a different circuit is required
• If Ra << Rb the mark-space ratio is almost 1:1 and T = 1.4 Rb C (e.g Ra = 1k, Rb = 47k etc)
• The output of the 555 can source or sink up to 100mA

### NOR Gate astable

The circuit shown is a NOR gate astable. The astable produces a clean square wave (mark-space ration = 1:1). The calculation of the time period depends on the types of logic gates used as different families of logic gate have different threshold voltages.

For CMOS gates T = 1.6 R C although this is just an approximation. It is best to make R variable so that the required time period can be achieved!

In operation, Q will be permanently high when the Enable is held high. When Enable falls low, the astable will oscillate.

### Some Examples and Exercises

1. Calculate the values required for a 555 based astable to oscillate at 100Hz.

• f=100Hz requires T=0.01s
• No requirement for mark-space ratio is required and so we are free to choose.
• It is easier to choose the capacitor value as we have a wider choice of resistors.
• Choose C=10µF (just a guess)
• Calculate Rb=115 ohms. This is too small, go back and guess a better capacitor
• Choose C=10nF (an informed guess)
• Calculate Rb=714k. This is better but not convenient.
• Choose C=22nF (a better guess)
• Calculate Rb=324k, use 330k - good enough!

2. Calculate the appropriate timing components to make the following astables:

• f=500Hz
• T=2s
• f=20kHz
• T=3ms
• f=12Hz
• T=5µs