Logic gates are digital devices. They have one or more inputs (labeled A, B, C etc) and one output (always labeled Q). The output only depends on the inputs. Logic gates are active devices which means they need a power supply although, for clarity, this is never shown on the circuit diagrams. The output is 0 V for Logic 0 and the supply voltage for Logic 1.

The output of a logic gate can supply a small amount of current, nominally 10 mA although some can provide more. The output can drive a low power LED directly (with a suitable series resistor), however, for larger output currents a transducer driver should be used.

Logic gates all have symbols and these should be learned. The action of a logic gate is described by a **truth table**. A truth table lists all the possible combinations of inputs (Low = 0 and High = 1) and the corresponding output. Truth tables should also be learned. Most logic gates can be modeled (using switches and resistors or light bulbs) which suffice as thinking tools but these models do not necessarily represent how a logic gate actually works.

The NOT gate shown has a single input and is represented by a triangle and a small circle. The circle is the NOT gate, the big triangle just means you can find it. On other gates, adding a small circle to the symbol is all that is required to add the NOT function. The output is Logic 1 when input A is Logic 0. The output is Logic 0 when the input A is Logic 1.

In the equivalent circuit shown, A = 0 when switch A is open (as in the diagram) and A = 1 when switch A is closed. When the switch is open (A = 0) then the resistor ensures Q is connected to +Ve and the output is Logic 1. When the switch is closed (A = 1) then Q is connected directly to 0 V and so the output is Logic 0.

The AND gate shown has two inputs. The output is only Logic 1 when input A **AND** input B are both Logic 1, otherwise the output is Logic 0.

If there are more than 2 inputs then all the inputs have to be Logic 1 to make the output Logic 1. If any of the inputs are Logic 0, the output is Logic 0.

In the equivalent circuit shown A = 0 when switch A is open (as in the diagram) and A = 1 when switch A is closed. Both the switches need to be closed (A = 1 and B = 1) to connect Q to +Ve and make the output Logic 1. If either switch is open then the resistor ensures Q is connected to 0 V and the output is Logic 0.

The OR gate shown has two inputs. The output is Logic 1 when input A **OR** input B **OR** both inputs are Logic 1, otherwise the output is Logic 0. The output is only Logic 0 when both inputs are Logic 0.

If there are more than 2 inputs then all the inputs have to be Logic 0 to make the output Logic 0, if any, or all, of the inputs are Logic 1, the output is Logic 1.

In the equivalent circuit shown A = 0 when switch A is open (as in the diagram) and A = 1 when switch A is closed. Either switch needs to be closed (A = 1 or B = 1) to connect Q to +Ve and make the output Logic 1. If both switches are open then the resistor ensures Q is connected to 0 V and the output is Logic 0.

The NAND gate shown has two inputs. The output is Logic 0 when input A **AND** input B are both Logic 1, otherwise the output is Logic 1. This is the exact opposite of an AND gate. The NAND gate is effectively an AND gate followed by a NOT gate, represented on the symbol as a small circle. **NAND** is therefore **N**ot **AND**, hence the name.

If there are more than 2 inputs then all the inputs have to be Logic 1 to make the output Logic 0. If any, or all, of the inputs are Logic 0, the output is Logic 1.

In the equivalent circuit shown A = 0 when switch A is open (as in the diagram) and A = 1 when switch A is closed. Both switches need to be closed (A = 1 and B = 1) to connect Q to 0 V and make the output Logic 0. If either switch is open then the resistor ensures Q is connected to +Ve and the output is Logic 1.

The NOR gate shown has two inputs. The output is Logic 0 when input A **OR** input B **OR** both inputs are Logic 1, otherwise the output is Logic 1. This is the exact opposite of the OR gate. The NOR gate is effectively an OR gate followed by a NOT gate, shown on the NOR gate symbol as a small circle. **NOR** is therefore **N**ot **OR**, hence the name.

If there are more than 2 inputs then all the inputs have to be Logic 0 to make the output Logic 1, if any, or all, of the inputs are Logic 1, the output is Logic 0.

In the equivalent circuit shown A = 0 when switch A is open (as in the diagram) and A = 1 when switch A is closed. Either switch needs to be closed (A = 1 or B = 1) to connect Q to 0V and make the output Logic 0. If both switches are open then the resistor ensures Q is connected to +Ve and the output is Logic 1.

The EOR gate shown has two inputs and the symbol is very similar to the OR gate except for the extra parallel line near the inputs. The output is Logic 1 when input A is Logic 1 **OR** input B is Logic 1 **BUT not both at the same time**. The output is Logic 0 when the inputs are either both Logic 0 or both Logic 1. The output is Logic 0 when the inputs are the same as each other. The output is Logic 1 when the inputs are different. The EOR gate is therefore useful for detecting when two inputs either are, or are not, in the same state.

In the equivalent circuit the switches are SPDT types - single pole, double throw. This means they are not simply on or off but connected to the left hand side or connected to the right hand side as the diagram is drawn. When the switches are both to the left (as in the diagram) then A = 0 and B = 0. The output Q is connected to 0 V and the output is Logic 0. Similarly, if both the switches are in the right hand position then A = 1 and B = 1 and again the output Q will be connected to 0 V giving an output of Logic 0. If, however, the switches are in opposite orientations such that A = 0 and B = 1 or vice versa then the output Q is not connected to 0 V and so the resistor connected to +Ve ensures the output is Logic 1.

Logic gates can be tested using simple push buttons with pull down resistors as the inputs and an LED and series resistor to show the state of the output. A suitable circuit is shown below:

© Paul Nicholls

April 2016

Electronics Resources by Paul Nicholls is licensed under a Creative Commons Attribution 4.0 International License.